1. Field of the Invention
The invention relates to the field of semiconductor processing and, more particularly, the "front end" processing used for formation of isolation or field oxide regions and underlying channel stops.
2. Prior Art
In the fabrication of metal-oxide-semiconductor (MOS) integrated circuits, active devices such as field effect transistors are often separated on the substrate, one from the other, by field oxide regions. These relatively thick regions of silicon dioxide provide greater separation and hence less coupling between overlying conductors and the substrate, thereby reducing parasitic current paths. Often channel stops are formed in the substrate beneath these regions to further reduce parasitic current paths. In complementary MOS circuits, the field oxide regions and the underlying channel stops are particularly important since they reduce "latch-up".
Typically, field oxide regions are grown through local oxidation. Silicon nitride masking members are first formed on the substrate at the regions where active devices are to be fabricated and then the substrate is subjected to an oxidation step. The oxidation grows in the areas unprotected by the silicon nitride. This is described in U.S. Pat. No. 3,873,383.
Various processes are known for forming the field oxide regions in conjunction with channel stops. An early example of such processing is shown in U.S. Pat. No. 4,013,484, where fully aligned channel stops are formed. Another technique for providing channel stops through use of an ion implanted surface layer is described in "Surface Doping Using Ion Implantation For Optimum Guard Layer Design In COS/MOS Structures" by Douglas and Dingwall, IEEE Transactions on Electronic Devices (Vol. ED22), October 1975 beginning at page 849. One disadvantage to the processing described in this article is that the n-type and p-type regions of the channel stops are spaced apart thereby decreasing device density.
Another process is described in U.S. Pat. No. 4,282,648. Here one region is double doped (first with n-type dopant, then with a p-type dopant) to form the final channel stops beneath the field oxide regions. Still another process is described in U.S. Pat. No. 4,411,058. This self-aligned process employs a metal mask along with ion implantation to form the channel stops.
One problem associated with some prior art processing for forming the field oxides regions and channel stops is described in conjunction with FIG. 1.
As will be seen, the present invention provides a process for forming the field oxide regions and channel stops using relatively low energy ion implantation and where the implantations used to form the channel stops also form complementary wells for CMOS transistors. Transistors are formed in these wells without threshold adjusting ion implantation steps.